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[CI] Format code according to conventions (#25827)

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Format code according to conventions
This commit is contained in:
QMK Bot
2025-12-01 06:25:13 +11:00
committed by GitHub
parent 330a8597f8
commit 6ed61c65dd
92 changed files with 307 additions and 348 deletions
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2
platforms/chibios/bootloaders/rp2040.c
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@@ -30,7 +30,7 @@ void enter_bootloader_mode_if_requested(void) {}
// Needs to be located in a RAM section that is never initialized on boot to
// preserve its value on reset
static volatile uint32_t __attribute__((section(".ram0.bootloader_magic"))) magic_location;
const uint32_t magic_token = 0xCAFEB0BA;
const uint32_t magic_token = 0xCAFEB0BA;
// We can not use the __early_init / enter_bootloader_mode_if_requested hook as
// we depend on an already initialized system with usable memory regions and

2
platforms/chibios/drivers/analog.c
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@@ -145,7 +145,7 @@ static ADCConversionGroup adcConversionGroup = {
.smpr = ADC_SAMPLING_RATE,
#elif defined(USE_ADCV2)
# if !defined(STM32F1XX) && !defined(GD32VF103) && !defined(WB32F3G71xx) && !defined(WB32FQ95xx) && !defined(AT32F415)
.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
# endif
# if defined(AT32F415)
.spt2 = ADC_SPT2_CSPT_AN0(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN1(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN2(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN3(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN4(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN5(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN6(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN7(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN8(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN9(ADC_SAMPLING_RATE),

6
platforms/chibios/drivers/audio_dac_basic.c
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@@ -77,9 +77,9 @@ GPTConfig gpt7cfg1 = {.frequency = AUDIO_DAC_SAMPLE_RATE,
static void gpt_audio_state_cb(GPTDriver *gptp);
GPTConfig gptStateUpdateCfg = {.frequency = 10,
.callback = gpt_audio_state_cb,
.cr2 = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event. */
.dier = 0U};
.callback = gpt_audio_state_cb,
.cr2 = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event. */
.dier = 0U};
static const DACConfig dac_conf_ch1 = {.init = AUDIO_DAC_OFF_VALUE, .datamode = DAC_DHRM_12BIT_RIGHT};
static const DACConfig dac_conf_ch2 = {.init = AUDIO_DAC_OFF_VALUE, .datamode = DAC_DHRM_12BIT_RIGHT};

8
platforms/chibios/drivers/audio_pwm_software.c
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@@ -63,8 +63,8 @@ void channel_1_set_frequency(float freq) {
pwmChangePeriod(&AUDIO_PWM_DRIVER, period);
pwmEnableChannel(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1,
// adjust the duty-cycle so that the output is for 'note_timbre' duration HIGH
PWM_PERCENTAGE_TO_WIDTH(&AUDIO_PWM_DRIVER, (100 - note_timbre) * 100));
// adjust the duty-cycle so that the output is for 'note_timbre' duration HIGH
PWM_PERCENTAGE_TO_WIDTH(&AUDIO_PWM_DRIVER, (100 - note_timbre) * 100));
}
float channel_1_get_frequency(void) {
@@ -117,8 +117,8 @@ GPTConfig gptCFG = {
and the .interval counts from 64 downwards - audio_update_state is
called just often enough to not miss anything
*/
.frequency = 60 * 64,
.callback = gpt_callback,
.frequency = 60 * 64,
.callback = gpt_callback,
};
void audio_driver_initialize_impl(void) {

6
platforms/chibios/drivers/eeprom/eeprom_kinetis_flexram.c
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@@ -482,7 +482,7 @@ uint32_t eeprom_read_dword(const uint32_t *addr) {
void eeprom_read_block(void *buf, const void *addr, size_t len) {
const uint8_t *p = (const uint8_t *)addr;
uint8_t * dest = (uint8_t *)buf;
uint8_t *dest = (uint8_t *)buf;
while (len--) {
*dest++ = eeprom_read_byte(p++);
}
@@ -507,7 +507,7 @@ void eeprom_write_dword(uint32_t *addr, uint32_t value) {
}
void eeprom_write_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
uint8_t *p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {
eeprom_write_byte(p++, *src++);
@@ -538,7 +538,7 @@ void eeprom_update_dword(uint32_t *addr, uint32_t value) {
}
void eeprom_update_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
uint8_t *p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {
eeprom_write_byte(p++, *src++);

4
platforms/chibios/drivers/eeprom/eeprom_legacy_emulated_flash.c
View File

@@ -577,7 +577,7 @@ void eeprom_driver_erase(void) {
void eeprom_read_block(void *buf, const void *addr, size_t len) {
const uint8_t *src = (const uint8_t *)addr;
uint8_t * dest = (uint8_t *)buf;
uint8_t *dest = (uint8_t *)buf;
/* Check word alignment */
if (len && (uintptr_t)src % 2) {
@@ -606,7 +606,7 @@ void eeprom_read_block(void *buf, const void *addr, size_t len) {
}
void eeprom_write_block(const void *buf, void *addr, size_t len) {
uint8_t * dest = (uint8_t *)addr;
uint8_t *dest = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
/* Check word alignment */

2
platforms/chibios/drivers/flash/legacy_flash_ops.c
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@@ -171,7 +171,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) {
FLASH->CR |= FLASH_CR_PSIZE_0;
#endif
FLASH->CR |= FLASH_CR_PG;
*(__IO uint16_t*)Address = Data;
*(__IO uint16_t *)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if (status != FLASH_TIMEOUT) {

8
platforms/chibios/drivers/serial_usart.c
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@@ -27,12 +27,12 @@ static QMKSerialConfig serial_config = {
# else
.baud = (SERIAL_USART_SPEED),
# endif
.cr1 = (SERIAL_USART_CR1),
.cr2 = (SERIAL_USART_CR2),
.cr1 = (SERIAL_USART_CR1),
.cr2 = (SERIAL_USART_CR2),
# if !defined(SERIAL_USART_FULL_DUPLEX)
.cr3 = ((SERIAL_USART_CR3) | USART_CR3_HDSEL) /* activate half-duplex mode */
.cr3 = ((SERIAL_USART_CR3) | USART_CR3_HDSEL) /* activate half-duplex mode */
# else
.cr3 = (SERIAL_USART_CR3)
.cr3 = (SERIAL_USART_CR3)
# endif
};
#elif defined(MCU_RP) /* Raspberry Pi MCUs */

8
platforms/chibios/drivers/uart_sio.c
View File

@@ -82,13 +82,13 @@ static SIOConfig sioConfig = {
};
#else
static SIOConfig sioConfig = {
.baud = SIO_DEFAULT_BITRATE,
.baud = SIO_DEFAULT_BITRATE,
# if defined(MCU_STM32) && defined(USE_USARTV3)
.presc = USART_PRESC1,
# endif
.cr1 = UART_CR1,
.cr2 = UART_CR2,
.cr3 = UART_CR3,
.cr1 = UART_CR1,
.cr2 = UART_CR2,
.cr3 = UART_CR3,
};
#endif

2
platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
View File

@@ -20,7 +20,7 @@ static flash_sector_t first_sector = UINT16_MAX;
#endif // WEAR_LEVELING_EFL_OMIT_LAST_SECTOR_COUNT
static flash_sector_t sector_count = UINT16_MAX;
static BaseFlash * flash;
static BaseFlash *flash;
static bool flash_erased_is_one;
static volatile bool is_issuing_read = false;
static volatile bool ecc_error_occurred = false;

4
platforms/chibios/drivers/ws2812_pwm.c
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@@ -310,7 +310,7 @@ void ws2812_init(void) {
palSetLineMode(WS2812_DI_PIN, WS2812_OUTPUT_MODE);
// PWM Configuration
//#pragma GCC diagnostic ignored "-Woverride-init" // Turn off override-init warning for this struct. We use the overriding ability to set a "default" channel config
// #pragma GCC diagnostic ignored "-Woverride-init" // Turn off override-init warning for this struct. We use the overriding ability to set a "default" channel config
static const PWMConfig ws2812_pwm_config = {
.frequency = WS2812_PWM_TICK_FREQUENCY,
.period = WS2812_PWM_PERIOD, // Mit dieser Periode wird UDE-Event erzeugt und ein neuer Wert (Länge WS2812_BIT_N) vom DMA ins CCR geschrieben
@@ -328,7 +328,7 @@ void ws2812_init(void) {
.dier = TIM_DIER_UDE, // DMA on update event for next period
#endif
};
//#pragma GCC diagnostic pop // Restore command-line warning options
// #pragma GCC diagnostic pop // Restore command-line warning options
// Configure DMA
// dmaInit(); // Joe added this

3
platforms/chibios/drivers/ws2812_spi.c
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@@ -188,8 +188,7 @@ void ws2812_init(void) {
0,
WS2812_SPI_DIVISOR
# else
WS2812_SPI_DIVISOR_CR1_BR_X,
0
WS2812_SPI_DIVISOR_CR1_BR_X, 0
# endif
#else
// HAL_SPI_V2